Space Based Radar (SBR)

Digital Beamforming (DBF)

Digital beamforming (DBF) is a rapidly developing technology which is the most advanced approach to phased array antenna pattern control. When implemented at the array element level, DBF enables full utilization of the maximum number of degrees of freedom in the array. This can lead to significant improvements in beamforming of simultaneous multiple independent beams, adaptive pattern nulling, space-time adaptive processing (STAP), and direction finding (DF), compared to traditional analog array control techniques. Because of its flexibility, DBF may find use in a wide range of phased array antenna applications.

One near-term application for subarray-level DBF is in large, relocatable ground-based phased arrays for Ballistic Missile Defense (BMD) and theater air defense. Mid-term DBF applications include conformal arrays for low profile aircraft such as Unmanned Air Vehicles (UAV), Unmanned Combat Air Vehicles (UCAV), and in next-generation manned airborne reconnaissance platforms. Sensors aboard these airborne platforms would typically support Airborne / Ground Moving Target Indication (AMTI / GMTI) radar and Synthetic Aperture Radar (SAR) for Intelligence, Surveillance and Reconnaissance (ISR) mission applications.

Subarray-level DBF also applies to very large planar arrays for space-based radar, where very low power and extremely low mass density are key requirements for satellite applications.

Today's state-of-the-art DBF phased arrays are primarily of laboratory prototype quality, and employ digital receivers only at the subarray-level. This is due to challenges both with RF receiver hardware, including reduction of size, mass, and DC power consumption, as well as digital challenges that include increasing ADC sampling rate, implementing digital sub-banding and digital time delays, and processing enormous data loads associated with DBF algorithms.

Digital receiver (Rx) technology tailored for the DBF array application is a newly emerging avenue of research and development that will significantly impact architectural trends in DBF phased array antennas and enable accelerated implementation of DBF. DBF Rx technology will likely adopt many of the features found in today's state-of-the-art Multi-Function Radar (MFR) receivers and/or Electronic Warfare (EW) receivers. Currently, digital radar receivers include, but are not limited to the following features: RF receiver front-end for RF-to-IF or RF-to-baseband demodulation, Automatic Gain Control (AGC) for RF front-end protection against strong interfering signals, analog-to-digital converters (ADC) for bandpass or baseband sampling, and digital finite impulse response (FIR) filtering for decomposition of sampled signals into in-phase and quadrature (I/Q) components.

DBF Rx technology requires all of these core digital Rx capabilities, plus many others which are essential for digital control and optimization of phased array antenna patterns. These include, but are not limited to the following: FIR digital filtering for DBF Rx channel equalization to enable wideband array-level channel-to-channel calibration; use of either digital sub-banding schemes such as multi-rate digital filtering or implementation of fractional sample digital time delays, to enable wideband beamforming and adaptive nulling; pulse compression and data reduction techniques for radar processing; programmability of bandwidth vs. resolution for MTI / SAR mission flexibility; novel data formatting schemes optimized for fast complex-valued channel-level digital processing; a high degree of built-in programmability for implementation of advanced algorithms for beamforming, channel filtering and sub-banding; module-level digital self-registration capabilities with respect to the system-level distribution and temporal aligning of digital clock and synchronization signals, coherent phasing of RF local oscillator (LO) signals, and array channel calibration RF pilot tones; and module-level self-assessment capabilities that monitor the overall in-situ performance of the DBF Rx array channel. The use of miniturized modular tile-like packaging concepts is also desired in order to advance the state-of-the-art of low-profile DBF phased array architectures that are both scalable and modular.

Recent trends in DBF Rx technology development have utilized commercial off-the-shelf (COTS) standardized VME and VXI electronic mainframes and circuit boards which support a modular building-block approach to DBF system implementation. In many cases, however, it is desirable to implement DBF in a much smaller volume and with a much lower mass density. One concept now being explored by AFRL/SN is the layered integration of a planar digital signal processor architecture with a planar DBF phased array architecture, using modular tile-based DBF Rx technology in the interface between the array and processor layers. One potential benefit of this modular, scalable approach is the reuse of key electronic sub-systems across many different DBF arrays architectures. It is anticipated that the Air Force may achieve significant cost savings using modular DBF Rx components in scalable DBF phased array sensor architectures, with the most significant savings derived from reduced life-cycle system maintenance costs and multi-system amortization of non-recurring engineering costs of the modular array electronics.

The goal of the AFRL/SN X-Band Digital Beamforming Receiver program effort is to develop a new class of compact digital receiver technology tailored to handle the unique challenges of DBF at X-band. The primary emphasis of this effort will be to develop a new digital receiver architectural approach which adds several DBF-specific features and performance capabilities, while leveraging appropriate techniques and capabilities from the existing state-of-the-art of digital receiver technology used for radar and EW systems. DBF-specific capabilities that are of particular interest should include, but are not limited to the following: implementation of digital time delays; implementation of digital sub-banding; and implementation of module-level self-registration features that will allow a DBF Rx module to precisely adjust its timing of digital clock and synchronization signals, phasing of incident RF local oscillator signals, and phasing of RF calibrator pilot tones, injected at the module-level. This program seeks to establish new techniques and design approaches that can be used to implement these and other DBF-specific performance capabilities. These features should be organized into the following four (4) main sub-systems of the DBF Rx: a) RF sub-system, b) digital channelization sub-system, c) digital time delay and filtering sub-system, and d) digital self-registration sub-system. Engineering design trade analyses and design simulation and modeling performance analyses will be used to identify candidate approaches and to simulate the expected performance of all DBF Rx technology developed in this effort. This program also will rigorously demonstrate the validity of the new DBF receiver capabilities by the fabrication and testing of at least four (4), but preferably sixteen (16), prototype DBF receivers at X-band. The following basic guidelines, which are commensurate with the current state-of-the-art of digital receiver technology, shall serve as performance goals for this program: 1) RF Spurious Free Dynamic Range (SFDR): 72-84 dB; 2) Effective linear digital resolution: 12-14 bits; 3) Noise figure: 2-4 dB; 4) Continuous frequency tuning range: 8-12 GHz; 5) Instantaneous bandwidth: 200-1000 MHz; 6) Maximum length of digital time delays: 4 RF wavelengths at low end of tuning range; 7) Resolution of digital time delays: 0.125 RF wavelengths at high end of tuning range; 8) Digital clock jitter and ADC sampling synchronization: 2-10 picoseconds; 9) Number of digital sub-bands within instantaneous bandwidth: 20-100, of equal width; 10) DC power consumption: 1-5 W; 11) Physical Size: Not to exceed 1 x 4 x 4 inches.