Space Based Radar (SBR)

Architecture Enhance SBR On-Board Processor (AESOP)

The goal of SBR operation for GMTI, SAR, and DTED detection of tactical targets from space promises great advantages to the warfighter. However, the technical challenges in achieving this goal are substantial. This is especially true for reliable, cost-effective, real-time OBP in a space environment; where OBP is defined here as: digital beamforming, adaptive jammer and clutter cancellation, image formation processing, target detection, and data formatting for transmission over tactical data links. In order to reduce risk on ongoing SBR programs, be technically achievable, affordable and reliable, the Air Force needs to reduce technical risk by developing severable hardware and software architectures that are proven from the perspectives of performance, schedule, cost and on-orbit maintainability.

The following areas of research and development have been identified as important risk factors for developing an extensible open architecture SBR OBP: 1. A multi-processor architecture that combines power efficiency, real-time performance, fault-tolerance, reliability, and cost-effective programming. 2. A radiation tolerant/hard design suitable for development, testing, and qualification in a representative space radiation environment, to include detection of single event upsets and minimizing their impact on operational performance. 3. The ability to migrate to new technologies so that the contracted R&D efforts can be efficiently and cost-effectively transitioned to future space surveillance systems, and updated with the latest technology before integration into an operational system. 4. An open interface, as demonstrated by integration with existing SBR ESA/OBP contractors under the Space & Missile Command (SMC) PRDA (Reference YS03-01). 5. The design, development, validation and implementation of GMTI, SAR, and DTED real time processing algorithms, including the interrelation of the algorithms, processing and the tactical datalink. 6. The verification of techniques for Space Time Adaptive Processing (STAP) to the extent necessary to reduce the effects of clutter and electromagnetic interference, on the efficient detection of fixed and moving tactical targets. There should be no proprietary Rights claimed for the computer architecture, hardware, software, algorithms or associated supporting infrastructure. Government purpose license rights or other rights that allow unrestricted Government and Government Contractor access to the design information are required for the hardware and software. This includes any hardware description language such as VHDL or Verilog and all software used in or to support this development. Integrated Circuit (IC) layouts may be based on proprietary cell libraries.