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Electronics (U)

Overview (U):

(U) The goals of this subthrust are to permit increased space system affordability, reliability, operability, and autonomy by developing high-performance, low-cost space electronics that satisfy customer requirements. These goals will be achieved by:

1. (U) Developing and demonstrating essential DoD space electronics (e.g., 32-bit processors, space qualifiable parallel architectures, or memory) with "spin-off" use by NASA and commercial programs.
2. (U) Improving direct information transmission to field commanders by 100% and reduce integration time 50% through advanced common electronics (e.g., signal processing systems).

(U) Key developments to meet the above goals are to:
1. (U) Provide at least a 10X improvement in AF space electronic system capability in the next five years by:
a. (U) Leveraging from the rapid progress being made in the commercial electronics industry.
b. (U) Transitioning high-demand commercial components into space qualifiable versions.
c. (U) Leveraging industry's huge investment in fabrication, design, software, and testability.
d. (U) Developing innovative hardening technologies and transferring to industry.
e. (U) Building standardized space data acquisition and signal processing modules by standardizing hardened implementations of selected commercial processors.
2. (U) Demonstrating space-qualifiable versions of commercial high speed data busses including the FDDI and the ATM.
3. (U) Develop new computer architectures and standards to reduce the customer's cost to develop and test systems by up to 50 percent.
4. (U) Provide more affordable computing solutions by enabling scaleable processing architecture and distributed computing.
5. (U) Develop space qualifiable Microelectromechanical System (MEMS) components to reduce the weight, size, power requirements, and heat load of satellites, enabling more functional, and autonomous large satellites and new classes of micro- and nano-satellites.

Description (U):

(U) The areas (and high-level goals) that make up the Electronics subthrust are:

1. (U) Packaging and Integration: focuses primarily on advanced packaging and high-density interconnect technologies as well as demonstrations of the benefits accrued from employing these technologies.

2. (U) Wafer Scale Integration/Advanced Packaging (WSI/AP): focuses on substrates, circuits, and packaging structures for advanced microelectronics that are inherently space qualifiable. The goal is to provide dramatic reductions in size, weight, cost, and potentially power consumption, while improving performance and reliability. One part of the work has targeted the development of a low-cost 3-D packaging system that has a 10X-50X density improvement over ordinary SEM-E boards. This approach, referred to as Highly Integrated Packaging and Processing (HIPP), is compatible with the unique thermal management problems in spacecraft, as well as the need to minimize contribution to spacecraft contamination through outgassing products in modern packaging materials. Since it has been impossible to provide an all-radiation hard parts strategy to USAF spacecraft due to sheer cost limitations, more efficient shielding approaches are under research that directly integrates into this approach and minimizes added mass per component on a subsystem basis. Cost reduction in the basic substrate technologies has been found to be problematic, and significant effort has gone into developing a no-compromise substrate technology with half the weight and one-fifth the cost of previous approaches. Our efforts have led to the development of the most complex plastic high density interconnect module to date, still smaller than a postage stamp, that will be demonstrated in a NASA mission.

3. (U) Ultra High Density Interconnects (UHDI) for Space Components: as a companion effort to the more developmental packaging research, UHDI focuses on achieving wholesale density accelerations in planar packaging technology to provide 10X density improvements over basic multi-chip module (MCM) technologies as required for high capacity solid state recording applications, micro/nano-satellites, and obviously the entire base of existing space electronics research. UHDI furthermore addresses the problem associated with geometric increases in the number of conductors in newer integrated circuits. As predicted by Rentís rule, systems within the next decade may have components with over 5000 conductors, versus the typical 200-300 today for complex integrated circuits. The new approaches will allow be compatible with HIPP, allowing a ten-fold enhancement in density. UHDI will achieve these impressive metrics through: (1) use of improved dielectric-metal interconnections, allowing patterned overlay approaches to improve wiring density dramatically; (2) thinned semiconductors and integral passives, which will allow total assemblies to made paper thin, permitting 200 circuit layers per inch; and (3) the innovation of spanning vias that permit tremendous communications bandwidth between assembly.

User Impact (U):

(U) None.

Programmatics (U):

(U) Concept/Technology.

Images (U):

(U) None.

Related Initiatives (U): None.

Related Requirements (U):None.

Related Categories (U):
Space Mission TechnologySpace Mission Technologies
This Table Is Unclassified.

Road Map Placements (U):

This Table Is Unclassified.

Requirements, Funding and Additional Hotlinks (U):

RDT&E Budget Item Project 8809
RDT&E Budget Item Project 2181
This Table Is Unclassified.

Lead Office (U):

(U) Air Force.

Point of Contact (U):

(U) Maj Mike LaPointe, NSSA, Open Phone: (703) 325-6422, DSN 221-6422.
(U) National Security Space Road Map Team, NSSA, Open Phone: (703)808-6040, DSN 898-6040.

Date Of Information (U):

(U) 16 July 1997

(U) Road Map Production Date: 12 July 1999

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